David Fried, vice president of computing products at Lam Group, was interviewed by industry media semiconductor Engineering (SE) to discuss and share his views on topics such as chip scaling, transistors, new architectures and packaging. The following is an excerpt from the original interview.
Q1: IC scaling has been a means of advancing design advancements in the chip manufacturing industry for decades. However, the costs associated with it have been climbing, and the benefits of shrinking size have diminished on a per-node basis. What do you think of Moore’s Law? Do we need 2nm or even more advanced processes? Need more computing power?
Dr. Fried: A 10-fold increase in computing power is not too much. Because everything requires computing power, including each user interaction point, storage point and node for each calculation, higher computing power is always useful, and the demand for computing power is endless. The current telecommuting and long-term stay at home further drive the demand for computing power.
Q2: In addition, in terms of comprehensive power, performance, area, cost and time, etc., the entire industry seems to have encountered some challenges in Transistor scaling, specific issues include power wall, RC delay and area scaling. What challenges have you encountered in this regard?
Dr. Fried: PPAY (power, performance, area and yield) or PPAC (power, performance, area and cost, if we want to be specific about cost) has always been an unavoidable element of all product development. We are always trying to overcome the hurdles associated with it and are always constrained by PPAC or PPAY. Our goal is to drive holistic development across all elements, but sometimes breakthroughs in one area may be more pronounced. But our challenge comes from a different combination, because the overall system performance improvement is the most important thing. Looking back at the history of development, sometimes a huge improvement in system-level performance can be achieved simply by adjusting the chip clock frequency, but sometimes it is necessary to do this through power management techniques. In any case, the most critical elements we face are power, performance, area, and yield or cost, which means that progress must be made in at least one of these areas to drive overall system performance improvements, and the “domain” in this sentence “It’s constantly changing.
Baseline transistor scaling has always been a big driver of overall system performance in my opinion, and upgrades here can be in any form, including incremental performance improvements, power performance, or uniform transistor scaling and enhancement consistency. Looking at it now, transistor scaling is clearly still very necessary, and this is reflected in many ways. For example, even if it’s not an increase in performance per se, scaling to increase density is worth the effort, because then we can increase core performance for the same area. Some people may not care about the performance gains of the transistors themselves. However, if you can increase the core performance of the GPU by, say, 10% through transistor scaling, that alone can give you a big step forward in system performance, because many data interactions that previously needed to be processed externally can now be done within the core. , so the processing speed will be greatly improved. That said, huge system-level improvements can also be achieved simply by scaling to improve monolithic integration. However, we still have to face the previous constraints and have been making efforts in all aspects. In any case, the ultimate goal remains the same, which is to achieve system-level performance improvements. Therefore, some of the approaches we take based on PPAC or PPAY have not changed much as a whole, and there is no “inflection point” for change. Today, we are still trying to break through in some areas and thereby improve system-level performance. As long as the market demand remains, we can provide higher computing power and storage.
Q3: Since 2011, the whole industry has shifted from planar transistors to a new generation of FinFETs. Chipmakers are still developing FinFET transistors at advanced nodes today, including 3nm FinFET and 3nm/2nm all-around gate nanochip transistors. How do you view this situation?
Dr. Fried: The transition from planar transistors to FinFETs is primarily a transition caused by the limitations of shrinking gate lengths. To better control device electrostatics, the entire industry has turned to dual-gate architectures, which involve gate scaling of a few nanometers and further create new dimensions of transistor scaling. We can increase the height to make the same package area have a larger effective width, which can make the whole transition smoother. The benefit of the all-around gate is full control of the device’s electrostatics, which results in an extra few nanometers of gate scaling. And it’s these few nanometer differences that open up new scaling dimensions. If in the future we can implement complementary FETs – such as nFETs and pFETs stacked on top of each other – this will give us additional logic scaling benefits.
We started by gaining the electrostatic control advantage to enable gate length scaling and thus created a whole new dimension of scaling. Nonetheless, the transition from FinFETs to all-around gates (nanowires or nanosheets) may not be as smooth as it used to be, because the new architecture requires us to perform processes below the structure, which is a very large and challenging change. In the era of FinFETs, we need to perform better semiconductor processes on the sidewalls, but we can still see the whole process. In the all-around gate nanosheet/nanowire structure, the structures involved in the processing will not be visible, making the measurement much more difficult. Therefore, the transition to the all-around gate is more challenging.
Q4: What do you think of alternative architectures such as advanced packaging and monolithic integration?
Dr. Fried: We should welcome any innovation at the system level, including transistor scaling, chip architecture improvements, and 3D integrated packaging, all of which are combined to meet the highest system performance requirements. The demand for systems in the current market is very diverse. In the past, the market was not so differentiated. At that time, everything was CPU-focused. Looking back, our approach to system-level performance improvement was a lot like a Swiss Army Knife, meaning that all approaches, whether corresponding to transistors, interconnects, packaging, or integration, served a larger overall approach.
Today, market needs have diversified, and each system has its own unique needs. If we go down these diverse paths, we may need to make a different approach in each area of transistors, packaging and interconnects, which means optimizing each system in a different way. For example, the memory, I/O, and compute unit configuration of one 3D integration solution may be completely different from that of another because different systems have different requirements and needs. There are a lot of things to choose. Once the chip architecture changes, the related technology, packaging and interconnection methods will also change. I’m looking forward to seeing how such diverse system performance requirements can change the industry.
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