Regarding the parallel connection of SiC MOSFETs, Infineon has successively released a lot of technical materials to help you better understand and apply. This article will use the device SPICE model and the Simetrix simulation environment to analyze the current sharing characteristics of a single SiC MOSFET under parallel conditions.
Simulation is not a substitute for experiment and is for reference only.
1. Select the simulation research object
IMZ120R045M1 (1200V/45mΩ), TO247-4pin, two parallel
1EDI40I12AF, single channel, magnetic isolation, drive current ±4A (min)
2. Simulation circuit Setup
As shown in Figure 1, based on the idea of double pulses, a main circuit and a driving circuit with two parallel tubes are built, and relevant stray parameters are set, and the ambient temperature is room temperature.
External main circuit: DC source 800Vdc, bus capacitor Capacitor (including parasitic parameters), stray inductance Ldc_P and Ldc_N between bus capacitor and half-bridge circuit, double pulse inductance Ls_DPT
Parallel main circuit: the whole is a half-bridge structure, double-pulse drives the lower bridge SiC MOSFET, and commutates with the upper bridge SiC MOSFET Body Diode. The lower bridge is two IMZ120R045M1s Q11 and Q12, which are connected in parallel through their respective emitter (source) inductors Lex_Q11 and Lex_Q12, and their respective collector (drain) inductors Lcx_Q11 and Lcx_Q12; the same is true for the parallel structure of Q21 and Q22 of the upper bridge Also a similar connection.
Parallel drive circuit: Based on the Kelvin structure of TO247-4pin, the power emitter and the signal emitter can be decoupled from each other. In addition, the 1EDI40I12AF driver chip is equipped with OUTP and OUTN pins, so the driver part of each single tube has The respective Rgon, Rgoff and Rgee (emitter resistors) are connected in parallel with the corresponding pins of the secondary side of the driver IC.
Drive part settings: Adjust the gate voltage Vgs=+15V/-3V by adjusting the secondary side power supply and voltage regulator circuit of the driver IC, and then set the gate resistance Rgon=15Ω, Rgoff=5Ω, Rgee is first approximately set to 0Ω (1pΩ) , plus the PCB trace inductance between the gate of the single Transistor and the driver IC.
Figure 1. Schematic diagram of double-pulse circuit based on TO247-4Pin SiC double-tube parallel connection
3. Parallel dynamic current sharing simulation
The dynamic current sharing of SiC MOSFETs in parallel is similar to that of IGBTs, except that SiC MOSFETs switch faster and are more sensitive to some parallel parameters. As shown in Figure 2, we first analyze the dynamic current sharing characteristics and influencing factors of the lower bridge Q11 and Q12 during the double-pulse switching process:
Figure 2. Schematic diagram of the double-pulse circuit with the lower bridge SiC double tubes in parallel
3.1 The influence of the external power source inductance Lex of the device on the parallel switching characteristics
Set Lex_Q11=5nH, Lex_Q12=10nH, other parameters and simulation results are as follows:
Figure 3. Parallel Current Sharing Simulation Results for Different Lex Inductors
3.2 The influence of the external power drain inductance Lcx of the device on the parallel switching characteristics
Set Lcx_Q11=5nH, Lcx_Q12=10nH, other parameters and simulation results are as follows:
Figure 4. Parallel Current Sharing Simulation Results for Different Lcx Inductors
3.3 Influence of the external gate-level inductance Lgx of the device on the parallel switching characteristics
Set the gate-level inductance Lgx_Q11=20nH, Lgx_Q12=40nH, where the gate-level inductances of Rgon and Rgoff are both Lgx, other parameters and simulation results are as follows:
Figure 5. Parallel Current Sharing Simulation Results for Different Lgx Inductors
3.4 The influence of the external source circulating inductance Lgxe and circulating resistance Rgee of the device on the parallel switching characteristics
In the case of asymmetric Lex inductance (no current sharing), set different source suppression inductance and resistance Lgxe=20nH, Rgee=1Ω and 3Ω to see the suppression and current sharing effect on the driving circulating current. The simulation results are as follows:
Based on the above simulation conditions and results of the TO247-4pin SiC MOSFETs in parallel, we can draw some preliminary conclusions as follows:
1. The difference in the source inductance Lex of the single transistor in parallel is very sensitive to the current sharing between the turn-on and turn-off of the SiC MOSFET. Because the difference in source inductance will also couple to the drive loop to further affect current sharing. As shown in Figure 8 below, taking turn-off as an example, due to the different source inductance Lex, the potential difference between the source circulating current and the source (VQ11_EE-VQ12_EE) is caused, which pushes up the Q11 source voltage VQ11_EE and indirectly reduces the Q11 gate level. and the voltage Vgs_Q11 between the source.
2. The difference of the drain inductance Lcx of the single tube in parallel has a significantly lower impact on the current sharing than the source inductance. Because the drain inductance does not directly affect the source circulating loop formed by the auxiliary source and the power source.
3. The difference of gate inductance has no obvious influence on dynamic current sharing, and the waveform of driving voltage Vgs has almost no change. If the total stray inductance of the main loop is reduced, and the gate resistance is reduced at the same time, so that the SiC works in a faster di/dt and dv/dt environment, the influence of the gate inductance on the current sharing may be slightly more obvious at this time. .
4. The auxiliary source resistor Rgee is not very effective in suppressing source circulating current and improving dynamic current sharing.
Here is another question: Since Rgee has a general effect on suppressing the source circulating current, what if a little Cge capacitance is added to the gate? Take a look at the following simulations:
It can be seen from the above simulation that the Cge capacitor has almost no effect on the turn-off, and the Cge is only turned on at a slower turn-on speed, increasing Eon and reducing the turn-on current oscillation, but for the turn-on current sharing difference and loss difference. , the impact is not large.
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