Home » Electronic News » When the size is shrinking, what can be used to break through the 2nm barrier?

When the size is shrinking, what can be used to break through the 2nm barrier?

Posted by: yiernuolashes 2022-07-22 Comments Off on When the size is shrinking, what can be used to break through the 2nm barrier?

The industry needs new interconnect solutions and new processes

to advance to the next process node

Chip makers may find a solution

but if you can’t find

Traditional chip size reduction may not help

Chipmakers have continued to make progress in Transistor technology at the latest process nodes, but the interconnection scheme between these structures has been lagging behind and has not kept pace with the development of transistor technology.

The chip industry is working on several technologies to address the interconnect bottlenecks, however, many solutions are still in the R&D stage and may take a long time to emerge – possibly until the 2nm process node before interconnect technology becomes available Breakout, 2nm is expected to launch sometime in 2023/2024. In addition, new interconnect solutions require the use of new materials and expensive processes.

Before the introduction of 2nm, the semiconductor industry needs to continue to solve several problems in advanced process chips: transistors, contacts and interconnects. Among them, the transistor is located at the bottom of the structure and acts as a switch for the signal. The interconnects sit on top of the transistors and consist of tiny copper wires that carry electrical signals from one transistor to another. Today’s advanced process chips have 10 to 15 layers, each of which contains a complex copper interconnect scheme using tiny copper vias to connect the layers.

Additionally, the transistor structures and interconnects are connected by a layer called the midline (MOL). The MOL layer consists of a series of tiny contact structures.

When the size is shrinking, what can be used to break through the 2nm barrier?

BEOL (copper interconnect layer) and FEOL (transistor level)

Source | Wikipedia

Less than a decade ago, at 20nm and 16nm/14nm, transistor problems at advanced nodes began to emerge, when copper interconnects in transistors became more compact, causing unnecessary resistance-capacitance (RC) delays in the chip. In short, it’s harder to get current to flow through tiny wires. Over time, chipmakers have now been able to simultaneously scale transistors and interconnects to the latest nodes – 7nm/5nm. However, at each node, complex interconnect schemes become a larger percentage of chip latency.

“As transistors shrink in size, the metal lines connecting them must also shrink in tandem in the overall high-level architecture of the multilayer interconnect stack,” explains Nerissa Draeger, University Program Director at Lam Research. “As successive generations of processes have progressed, these local local interconnects have become narrower and closer together, causing today’s copper interconnects to face enormous challenges for further scaling. For example, further reductions in line width or The height of the wire will greatly increase the resistance of the wire.”

Many of these problems can be traced back to the way copper interconnects are made. To do this, chipmakers use a so-called copper dual damascene process (dual damascene process) in their manufacturing plants. The process was developed by IBM in the late 1990s, almost 25 years ago when chipmakers started using dual damascene at 220nm/180nm and have since scaled the technology with process size.

Over time, chipmakers have gradually advanced the technology to more advanced nodes, with plans to extend it to 3nm. However, below 3nm, the RC delay problem may become more problematic, and as a result, the industry may need a new solution.

Finding the next generation of interconnect technology is critical. Interconnect technology needs to go hand in hand with innovations in transistor technology, which are critical to scaling chip process sizes. But if the industry fails to develop the next generation of cost-effective interconnects for 2nm, the chip scaling we’ve been doing today could stall.

Various new interconnect technologies currently in development for 2nm and below process nodes include:

Mixed metallization or prefilled.This combines different damascene processes with new materials to enable smaller interconnects and thus lower latency

Half Damascus craft. A more radical approach, using subtractive etching, enables tiny interconnects.

Super vias, graphene interconnects and other technologies. These are in the R&D stage as the industry continues to look for alternative metals to copper.

Each proposed R&D technology presents its own challenges. As a result, the chip industry is betting on both sides, seeking breakthroughs in interconnect technology on the one hand, and alternatives to develop new system-level designs on the other. Advanced packaging is one of the alternatives, and it is expected to continue to gain industry attention regardless of how scaling of chip process dimensions progresses.

From aluminium to copper

During chip manufacturing, transistors are fabricated on wafers in a fab. The process takes place in the front-end (FEOL) of the fab. Then, the interconnect and MOL layers are formed in a separate fab facility called the back-end (BEOL).

Until the 1990s, aluminum-based interconnects were integrated into chips. However, by the late 1990s, as chip process sizes approached 250nm, aluminum began to fail to withstand higher device current densities.

So by the late 1990s, starting at the 220nm/180nm node, chipmakers migrated from aluminum to copper. According to IBM, copper interconnects have 40 percent lower resistance than aluminum, which helps improve chip performance.

In 1997, IBM announced the world’s first copper interconnect process based on 220nm technology. This process, known as dual damascene, became the standard method for making copper interconnects in chips and is still used today.

Initially, chips had only six layers of interconnection. At the time, 180nm devices had metal pitches of 440nm to 500nm, according to WikiChip. By contrast, by the 5nm node, the chip consisted of 10 to 15 layers of interconnects with a metal pitch of 36nm. According to the definition of TEL, metal pitch refers to the minimum center-to-center distance between interconnect lines.

When the size is shrinking, what can be used to break through the 2nm barrier?

Manufacturing Process of Double Damascus Process

(a) via patterning; (b) via and trench patterning; (c) barrier layer deposition and copper seed layer deposition; (d) copper electroplating and removal of excess copper by chemical mechanical polishing; (e) overlay layer deposition.Source: TU Wien/Institute of Microelectronics

In the dual damascene process, a low-k dielectric material is first deposited on the surface of the device. Based on carbon-doped oxide materials, a low-k film is used to insulate one part of the device from another.

The next step is to pattern tiny vias and trenches in the dielectric material. The vias/trenches are getting smaller and smaller with each node generation. Therefore, in today’s advanced process chips, chipmakers are using extreme ultraviolet lithography (EUV) to pattern vias.

At future nodes, vias will require EUV with multiple patterning capabilities. “The challenges of EUV multi-patterning are very similar to those encountered during the implementation of ArFi (193nm immersion),” said Doug Guerrero, senior technologist at Brewer Science. “Machine-to-machine coverage becomes critical if ArFi or EUV is used. From a materials point of view, the multi-patterning process always involves the integration of planarization layers. Planarization materials are also known as gap filling materials. They have to fill and planarize very narrow trenches with high aspect ratios.”

After this step, the pattern structure is etched out, forming vias and trenches. Then, using physical vapor deposition (PVD), a thin barrier material based on tantalum nitride (TaN) is deposited within the trenches. Then, a tantalum (Ta) liner material is deposited over the TaN barrier. Finally, the via/trench structures are filled with copper using electrochemical deposition (ECD). This process is repeated multiple times at each layer, resulting in a copper wiring scheme.

This process worked until 20nm when problems started to occur. At that time, the resistivity of copper in interconnects increased exponentially, causing chip delays. So, starting at 22nm and/or 16nm/14nm, chipmakers started making some big changes. On the interconnect side, many have replaced Ta as a liner with cobalt, which helps reduce resistance in the interconnect.

Likewise, at these nodes, chipmakers have moved from traditional planar transistors to next-generation finFETs, which offer higher performance at lower power.

Then, at 10nm, Intel took steps to reduce chip resistance. Intel’s 10nm process has 13 metal layers. Intel’s first two local interconnect layers are called Metal 0 (M0) and Metal 1 (M1), where cobalt is a conductive metal, not copper. The remaining layers use conventional copper metal.

Other chipmakers still use copper on the M0 and M1 layers. However, by 10nm/7nm, on the tiny contacts in the MOL, all chipmakers have moved from tungsten to cobalt, which can also help reduce line resistance.

Today, leading chipmakers have extended finFETs and copper interconnects to 5nm. To be sure, there will always be an industry demand for advanced process chips that can enable new and faster systems.

“There is no doubt that even for non-technical markets, being able to compute 10 times faster than today is not only commercially practical, but also a competitive imperative,” said D2S CEO Aki Fujimura. There is almost no end to the need for high computing power.”

Looking ahead, though, there are some troubling signs. The benefits of shrinking transistors are getting smaller and smaller with each new generation of nodes, and the RC delay problem is still lingering.

“At the 7nm and/or 5nm nodes, copper interconnects will likely be lined with a tantalum nitride barrier and cobalt,” said Griselda Bonilla, IBM’s senior manager of advanced BEOL interconnect technology research. “As dimensions shrink, the proportion of increased line resistance increases. , which accounts for a higher proportion of the total delay. The increase in resistance is driven by a number of factors, including a reduction in conductor cross-section, a further reduction in volume percent copper due to high resistivity barriers and liner layers not reducing with process scaling, and due to Increased resistance due to lossy electron scattering at the surface and grain boundaries.”

Towards 3nm and smaller process sizes

That hasn’t stopped the semiconductor industry from moving to the next node, though. Today, leading chipmakers are working on 5nm, 3nm/2nm and even smaller process sizes.

Samsung plans to use next-generation transistors, the gate-surround FET, on the 3nm process. TSMC plans to expand finFETs to 3nm, but will move to gate-surround FETs at 2nm.

FinFETs are approaching their physical limits when fin widths reach 5nm (equivalent to the foundry’s 3nm node). Gate-surround FETs have better performance, lower power dissipation, and lower leakage current than finFETs, but they are more difficult and more expensive to manufacture.

According to Imec, the metal spacing at 3nm is between 21nm-24nm. And at 3nm, chipmakers will continue to use traditional copper dual damascene processes on existing materials, which means that RC delays will still cause problems in chips.

“As we move to the 3nm node, we will see EUV with multi-patterning continue to scale BEOL at critical pitches of less than 25nm,” said Andrew Cross, director of process control solutions at KLA. “This continued pitch scaling will continue to affect line and via resistance, as the thickness of the barrier material scales less than the pitch.”

In the R&D area, the industry will continue to explore new technologies to help solve these and other issues at 3nm and lower process sizes. “At about 24nm metal pitch, we expect to start seeing some favorable design and material changes,” said Scott Hoover, senior director of strategic product marketing at Onto Innovation. “This includes fully self-aligned vias, buried power rails, super via integration schemes, and wider adoption of ruthenium linings.”

The power rail was developed in BEOL, a fine and tiny structure designed to handle the power supply network function in the transistor. Imec is developing the next generation of buried power rail (BPR) technology. The BPR developed in FEOL is buried in transistors to help free up interconnect routing resources.

In addition, the industry has also been exploring the use of ruthenium in the lining of interconnects. “Ruthenium is known for improved copper wetting and gap filling,” said IBM’s Bonilla. However, while ruthenium has excellent copper wetting, it has some other drawbacks, such as short electromigration lifetime and chemical mechanical polishing. Cell process challenges. This limits the use of ruthenium liners in the semiconductor industry.”

Other new, more promising interconnect solutions are on the horizon, but they may not appear until 2023/24 when the chip manufacturing process size reaches 2nm. According to Imec’s roadmap, the semiconductor industry can transition from today’s dual-damascene process to a next-generation technology called hybrid metallization at 2nm. Half Damascus and other schemes will be adopted in the future.

When the size is shrinking, what can be used to break through the 2nm barrier?

Picture transistor roadmap (top) and interconnect technology (bottom)

Source | Imec

All of this depends on several factors, namely the ability to develop new processes, materials and tools, and, of course, cost is also critical.

“No one thinks the current scheme will last for many generations,” said David Fried, vice president of computing products at Lam Research. “The expansion is done now through incremental improvements and a lot of work. There will be more significant changes in the future, but I expect them to be Will be introduced in a steady stream of evolving improvements. Obviously, reliability sets some major barriers to shrinking the interlayer dielectric constant k, but this barrier has continued to be lowered as technology advances. As filling materials change , the requirements for the lining will also change. The processes associated with these materials will present corresponding advantages in different integration schemes such as dual damascene, single damascene, fully self-aligned integration, and even subtractive metallization And disadvantages. After a few generations, the BEOL may look completely different than it does today, but I hope that this change is the result of a concerted incremental change in all these elements.”

Still, for the most closely spaced layers, today’s copper double damascene process will continue to scale to some extent. “Double damascene has always been an issue. Still, as long as we go beyond 26nm or 24nm, it’s still pretty much copper and cobalt territory. The tipping point is when you’re below 20nm. Below 20nm, there are a lot of pitfalls. Not only It’s only a matter of resistance, but there are also reliability issues, especially with copper.”

Therefore, roughly at the pitch corresponding to the 2nm node, the industry wants to migrate to a technology called mixed metallization. Some call it the prefill process. The technology will likely be used in the most closely spaced layers, but the less critical layers will continue to use traditional copper processes.

In a basic hybrid metallization process, you deposit a dielectric material on a substrate. Then, tiny copper vias and trenches are formed using a traditional Damascus process. Then, continue to repeat the process and form tiny vias and trenches.

However, mixed metallization does not use a dual damascene process, “it uses selective deposition of through-hole metal,” explains Tokei. “Molybdenum, ruthenium, or tungsten are metals that can be used to fill tiny vias. At the end, you have a regular copper metallization, which can be thought of as a single damascene process copper metallization.”

In the semiconductor field, the single damascene process is not a new process. “Dual Damascus process is smarter and more cost-effective than single Damascus process. As process size decreases, the challenge of dual Damascus process is to achieve defect-free copper metal in taller and narrower combined line and via openings change,” said Takeshi Nogami, a key member of the IBM research team. “The single-damascene process allows the two patterns to be metallized separately, making it easier to shrink the width and pitch dimensions, and to increase the line-to-width ratio to slow the rise in resistance.”

In summary, mixed metallization uses two different metals in the interconnect. “For 2nm, this makes a lot of sense,” said Imec’s Tokei. “Compared to the dual-damascene process, the through-hole resistance is lower. The reliability will increase, and at the same time, the low resistivity of the copper in the line can be maintained.”

However, there are some obstacles to mixed metallization. There are several different and difficult deposition techniques that enable the gapfill process. “The challenge is how to achieve good via fill uniformity without loss of selectivity,” MH said. TSMC researcher Lee, who published a paper at IEDM, noted, “Furthermore, the via sidewalls are unobstructed, Potential interactions between the via material and the underlying metal can cause reliability issues.”

What is Half Damascus?

  

Source | TweakTown

If the industry can address these issues, hybrid metallization can be inserted at the 2nm node. However, if chip size reductions are to continue, the industry may need another solution for sub-2nm.

The next step for the sub-2nm solution is what many call half-Damascus, a more radical technology for the tightest metal pitches. The semi-Damascus process is being studied by the semiconductor industry for a number of reasons.

Robert Clark, a senior member of the TEL technical team, said: “In the structure of the dual damascene process, the number of lines is the limiting factor for copper grain growth. Conversely, if the metal lines are formed by depositing a metal layer, it can be annealed and then formed by etching. metal wire, then the grain size can be increased. But with copper, this process is difficult to achieve. In this process, metals like ruthenium are easier to handle, so it has the potential to make what people call half-damascus Craftsmanship becomes possible.”

The starting point for the application of the half Damascus process is the pitch below 20nm. “Our goal is to advance the half-Damascus process to below the 18nm pitch, which is about four or five years from now in terms of the process node development route,” said Imec’s Tokei. “Half-Damascus is disruptive for a logic chip fab for copper metallization and dual damascene. Hybrid metallization fits naturally into the fab’s process flow, but you need some pre-processing New functionality that populates itself. For the rest, you can reuse everything in the fab.”

Half Damascus requires a different process with new tools. In short, half damascene enables tiny vias with air gaps, reducing RC delays in the chip.

The technique relies on metal patterning using a subtractive etch process. Subtractive etching is not a new technology and is used in older aluminum interconnect processes. However, there are some challenges to implementing the technology below 2nm.

“The half-Damascus process starts by patterning the vias and etching them into the dielectric film. Then, the vias are filled with metal and overfilled, which means the metal deposition continues until they are formed over the dielectric. One layer of metal. The metal is then masked and etched to form metal lines,” Tokei said in a recent blog post.

In the lab, Imec designed a 12-metal-layer device based on the 64-bit Arm CPU architecture. The device has two layers of metal interconnects using ruthenium, with air gaps between the metal lines.

“Air gaps show the potential to improve performance by 10 percent, while reducing power consumption by more than 5 percent,” Tokei said. “Using wires with high aspect ratios can reduce IR drops in the power delivery network by 10 percent for improved reliability.” .”

However, the Half Damascus is far from ready for practical use. “There are many potential problems with the half-Damascus scheme, such as alignment, metal etch, LER, leakage, chip-package interaction, seal ring compatibility, plasma damage, and routability,” Tokei said in a recent paper.

write at the end

Other interconnect technologies are also in development, such as super vias, hybrid metal-graphene interconnects, and copper replacements.

But to be sure, the industry prefers to extend the life of the copper-dual damascene process as long as possible due to several challenges facing the next-generation technology.

At some point, the semiconductor industry may have to use next-generation interconnect technology. Chipmakers may find a solution. But if they can’t be found, then traditional chip size reductions may be in vain, forcing the industry to find alternative solutions for more advanced chips.

This has already happened. The industry is increasingly calling for advanced packaging, an alternative that enables the development of advanced system-level designs and possibly more customization.

So far, though, the semiconductor industry is looking at both traditional chip scaling methods and advanced packaging to develop new system-level designs. Both approaches are feasible, at least for the foreseeable future.

  

The Links:   FS450R07A2P2_B31 LM64C09P