“This reverse engineering is often a time-consuming process that involves painstakingly removing the many nanoscale interconnect layers inside the chip and mapping them using different layers of imaging techniques, from light microscopy to larger features, to Electron microscopy looks at the smallest features.
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Translated from -spectrum, By Samuel K. Moore
Swiss and U.S. researchers use a non-destructive technique that can reverse engineer an entire chip without destroying it
Ptychographic X-ray tomography scans the entire chip or zooms in on specific points to reveal its circuitry
Scientists in Switzerland and California have come up with a new technique that can reveal three-dimensional designs of microprocessors without destroying their structure.
This reverse engineering is often a time-consuming process that involves painstakingly removing the many nanoscale interconnect layers inside the chip and mapping them using different layers of imaging techniques, from light microscopy to larger features, to Electron microscopy looks at the smallest features.
The inventors of the new technique, called ptychographic X-ray laminography, say it could be used by integrated circuit designers to verify that a manufactured chip conforms to their design, or by government agencies to verify that a chip may be secretly added to “kill switches” or hardware trojans in integrated circuits.
“It’s the only way to non-destructively reverse engineer an Electronic chip — not only that, but we’re making sure the chip is made as designed,” said Anthony FJ Levi, a professor of electrical and computer engineering at the University of Southern California. “It’s like A fingerprint to track the provenance of every manufacturing process.”
The new technology is an improved version of what the team released in 2017, and it’s called ptychographic [1]Computed Tomography. The process involves irradiating coherent X-rays from a synchrotron onto 10-micron pillars cut from sections of the chip. The team then recorded how the X-rays were diffracted and scattered at different angles on the pillars and calculated what the internal structure would look like to create the pattern.
Gabriel Aeppli, head of the Photonic Sciences Unit at the Paul Scherer Institute (PSI) in Switzerland, explained that the goal was to avoid any crystal cutting altogether. Gabriel Aeppli, who is also a professor of physics at the Swiss Federal Institute of Technology in Zurich and Lausanne, led the research. “A modern chip with 1 billion transistors has pins that are much larger than 10 microns. The team wanted to use a single technique that would allow them to image the entire chip and also zoom in on specific local areas.
Previous techniques required the wafer column because we were trying to penetrate the entire edge of the wafer, absorbing a lot of X-rays to produce a useful diffraction pattern. The X-rays hit the chip at an angle that creates a sufficiently small cross-section. However, it also produces informational errors. Aeppli explained that some information can be reassessed by making some assumptions about what you’re looking at. For example, we know that real interconnects cannot have specific shapes.
Aeppli also said that finding the right angle (61°) for the X-rays, balancing absorption and loss of information was a big problem.
The new technology is used to test chips made with 16-nanometer process technology. The scientists zoomed in on the red squares, then the blue circles, to progressively find smaller features.
In this new technique, the bare chip is ground to a thickness of 20 microns before being placed on a scanning stage tilted at 61°. While the X-rays are focused on the chip, the scanning stage rotates the chip. The resulting diffraction pattern is picked up by a photon counting camera. Using the technology in low-resolution mode, the team scanned an area of 300 by 300 microns in 30 hours.
They then zoomed in on the 40-micrometer-diameter section to generate a 3D image with 18.9-nanometer resolution, a process that took another 60 hours. Then, using the high-resolution patterns, the researchers were able to identify sections of individual inverter circuits in chips made with the 16-nanometer node technology.
This is the first tomographic microscope designed by PSI’s Mirko Holler and can take a 12mm x 12mm image, which can fit a lot of chips like the iPhone processor Apple A12, but is still a bit small for an entire Nvidia Volta GPU . Although the team tested the technology on chips made with the 16-nanometer process technology, it will be able to handle chips made with the new 7-nanometer process technology with ease, where the minimum distance between metal lines is about 35 to 40 nanometers. The team tested the technology on a chip using a 16-nanometer process technology, which it said will easily handle those that use a 7-nanometer process technology with a minimum distance between metal lines of between 35 and 40 nanometers.
The researchers say that future laminated imaging techniques could achieve a resolution of 2 nanometers, or reduce the detection time of low-resolution 300*300 microns to less than an hour.
Ptychographic X-ray laminography can Display the metal parts of the inverter[右].Shows a good fit with the circuit[中，左].
The biggest credit for these technological improvements is the new generation of synchrotron light sources. PSI’s synchrotron is considered a third-generation machine. Meanwhile, fourth-generation machines are already in operation, such as the MAX IV in Sweden. With a higher flux of X-ray photons passing through the chip, the system can collect more useful data per unit of time, resulting in higher resolution and faster processing. “We hope that over the next five to six years, we can increase the number of pixels we collect per unit of time by 1,000 to 10,000 pixels,” Aeppli said.
Improvements in Ptychographic X-ray tomography can be further accelerated by starting with more chip information. Knowing the design rules ahead of time allows the system to draw conclusions with fewer photons. One of the main uses that Aeppli envisions for the technology is to look for deviations from the design that could be manufacturing errors or other more dangerous effects.
“It’s easier to find deviations from a design than to reverse engineer the entire design,” Aeppli said. The United States has a lot of national security interest in this technology.
However, Aeppli expects chipmakers to use laminated imaging as well. “There are some national laboratories with synchrotrons in the immediate vicinity of every large chip fabrication facility,” he noted.
The new technology has been published in the journal Nature Electronics.
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